The present invention relates to a circuit arrangement with two or more circuit components that cooperate through a data transfer device, and in particular to an integrated circuit arrangement for transferring data between a data transmitter and a data receiver.
Circuit arrangements often have a digital and/or an analog/digital integrated circuit, and are generally referred to as mixed-signal ICs. A circuit arrangement with such a structure is illustrated in FIG. 1. The circuit arrangement includes a first circuit section 1, a second circuit section 2 and a data transfer device 3 between the first and second sections.
Referring still to FIG. 1, the first circuit section 1 designates the above-mentioned integrated circuit, which is embedded in the second circuit section 2, and which is connected to this by communication buses or connection lines. The second circuit section 2 can have output or bond pads. Output terminals, which form the interface of the circuit arrangement and thus of the integrated circuit to the outside world may be bonded on these bond pads. However, it would also be conceivable that the second circuit section 2 is also structured as an integrated circuit in which the integrated circuit of the first circuit section 1 is embedded. Circuit arrangements with such a structure are, for example, representatives of integrated circuits technically known as “cell-based systems” or “systems on silicon” or “circuits with embedded macros.” With integrated circuits of this kind, the first circuit section 1 (cell or embedded macro) frequently is an already-existing functional block, which is only embedded in a new environment (the second circuit section).
Both the first and second circuit sections 1, 2 typically need a fixed chip surface due to their functionality or their manufacturing technology, especially in the case of chip bonding, ESD protection, etc. Consequently, the chip surface cannot be further optimized without major interventions in the functionality or technology. However, the chip surface is often largely determined by the data transfer device 3 that is needed between the circuit sections. Particularly in very complex systems (e.g., signal processors, processors, microcontrollers, etc.) this can sometimes be much larger than the integrated circuit itself.
A typical data transfer device 3 is illustrated in FIG. 2. The device includes a data transmitter 10, a data receiver 12, and a data bus 17. The data transmitter 10 sends data via a first data buffer 16 and via the data bus 17 to a plurality N of data receivers 12-15. Each data receiver 12-15 has associated with it a second data buffer 18 and two memory devices 20, 22. The two memory devices 20, 22 associated with the data receiver 12 are arranged in a master-slave structure. During data transfer, this structure allows transfer of the data from the data bus 17 to the data receiver 12. This is made possible by a process controller 24 that opens the first memory device 20 acting as master, and does not close it until this memory device contains updated (i.e., valid) data. At this moment, under the control of the process controller 24, the first memory device 20 is closed, and the second memory device 22, acting as slave, is opened. This ensures that only valid, error-free data are read out on the receiver side.
However, for the data transfer device 3, the surface area needed for two memory devices 20, 22 becomes greater and greater as more receivers are connected to the data bus 17. As a result, and as a result of layout-based contingencies, the region associated with the data transfer device 3 (FIG. 1) often becomes disproportionately large compared to the integrated circuit 1 and the pad region 2. The problem of a double surface expenditure for two memory elements for each receiver consequently is often unacceptable, just for reasons of cost.
Therefore, there is a need for a circuit arrangement whose design optimizes the surface of the data transfer device.